1. Field of the Invention
The present invention relates to a circuit used to control hand-shake type data transfer.
2. Description of the Prior Art
Handshaking between digital devices is the process of exchanging control signals such as receive, transfer, and timing information to accomplish synchronized data transfer. Handshaking is often used between control circuits for the stages in a pipelined microprocessor. In most handshaking systems, a data transfer circuit is controlled by a control circuit.
An example of a conventional data transfer circuit with an associated control circuit is shown in FIG. 1. FIG. 1 shows a specific arrangement of a handshake system using a one shot D flip-flop as found in the prior art.
Shown in FIG. 1 are latch circuits 42 and 43. Latch circuits 42 and 43 are controlled by the control circuits 13 and 14 shown in the lower half of the diagram. Latch circuits 42 and 43 transfer input data sequentially as output data.
As shown in FIG. 1, a one-shot pulse circuit 41 comprising a D flip-flop is coupled to the input of control circuit 13. When a high level write request pulse "PUSH" signal (a data transfer request signal) is received at the clock terminal CLK for flip-flop 41, a high level Send signal S1 (a data transfer request signal) is provided from terminal Q of flip-flop 41 to control circuit 13. Control circuit 13 subsequently causes the data latch circuit 42 to transfer data in response to S1. Control circuit 13 also outputs a send signal S2 to control circuit 14. Control circuit 14 causes the data latch circuit 43 to transfer data in response to input signal S2. Subsequently, control circuit 14 transmits a new send signal S3 to the next control circuit. Transfer and latching is sequentially continued in a similar fashion from one stage to the next in a typical pipelined microprocessor.
Timing for the above operations in the conventional prior art circuit of FIG. 1 is shown in the timing chart in FIG. 2.
The data transfer system shown in FIG. 1 uses an asynchronous FIFO memory. As previously mentioned, a one-shot pulse is generated using the D flip-flop 41. Flip flop 41 is provided to control the input pulse width for a predetermined time for the send signal S1 resulting from the data transfer request signal "PUSH". If D flip-flop 41 is omitted, the signal "PUSH" and the signal S1 become the same. As will be explained hereafter, in case the pulse width of the signal "PUSH" becomes too long, "parasitic oscillations" will be created, whereby data will be recurringly transferred two or more times as a result of only one "PUSH" signal.
The parasitic oscillation phenomenon can be explained by reference to FIG. 3 and FIG. 1.
FIG. 3 is a timing chart which graphically demonstrates how parasitic oscillation takes place for the circuit in FIG. 1 in which the D flip-flop is omitted. In this case, the signal "PUSH" is used directly as the send signal S1 to control circuit 13 and is coupled to an input to NAND gate 44 shown in FIG. 1. Upon receipt of the "PUSH" signal, NAND gate 44 generates an output acknowledge signal, A1 and latching signal L1 which are turned into 0. Signal A1 causes pulse signal S2 to be generated at the output of NAND gate 45 in circuit 13 of FIG. 1.
Signal A2 from the succeeding stage 14 and signal IR from stage 13, which are both "0", are fed back to inputs to NAND gate 44. This causes output signal A1 to change back to "1". The change of A1 back to 1 causes A2 and IR to change back to "1". As can be seen from FIG. 3, if the active status of the "PUSH" signal extends for longer than a certain time (time t in FIG. 3), the signals A2 and IR will have turned into "1" again. Therefore, the signal A1 will be turned into "0" again, causing latch signal L1 to be generated two times with respect to one "PUSH" signal. As a result, the same data will be transferred twice to the succeeding latch circuit 43 by latch circuit 42.
This phenomenon is referred to as parasitic oscillation and cyclically repeats so long as the signal "PUSH" is being held at "1". Parasitic oscillation causes the same data to be transferred from the data latch circuit 42 on a recurring basis.
The problem of parasitic oscillation can be further appreciated by referring again to FIG. 1 which shows a send line S2 which is coupled between the output of NAND gate 45 and an input of NAND gate 47. Also shown is acknowledge line A2 which is coupled between the output of NAND gate 47 and an input of NAND gate 44. If, in FIG. 1, the pulse width of the data request signal, which is transferred in sequences of S1, S2, and S3, is too long because of the length of the send lines and return acknowledge lines, parasitic oscillations similar to that mentioned above are generated. For example, employing the leading edge of the signal S2, the pulse width for S2 is determined by the following expression:
Pulse width S2=(Wiring delay of the Send line S2)+(Propagation delay of the NAND gate 47)+Wiring delay of Ack line A2)+(Propagation delay of the NAND gates 44 or 46, whichever is longer)+(Propagation delay of the NAND gate 45)
Therefore, if the wiring lengths of the send line S2 and the acknowledge line A2 become too long, the delay time increases. The pulse widths of the data transfer signals S1, S2, and S3 cannot exceed the above-described pulse widths or parasitic oscillations will be generated.
In an attempt to restrict such parasitics oscillation and, more particularly, to limit the pulse width of the signal "PUSH" below a time duration so that no parasitic oscillation is generated, a one-shot pulse generation circuit which uses a D flip-flop is provided in a conventional circuit such as the one shown in FIG. 1.
However, problems remain even when a D flip-flop is used. As can be seen from the foregoing explanation, the D flip-flop circuit works properly only if the input pulse is kept below a certain width. Moreover, a conventional hand-shake system will have many stages so that the optimum pulse width may vary from stage to stage.
In addition, a conventional data transfer system faces other design problems when used in pipeline applications. For instance, a conventional FIFO memory as used in FIG. 1 typically uses a bipolar element having a large driving capacity. Sometimes, however, it is necessary due to design considerations, to use a MOS type element having a small driving capacity when high integration and low power consumption are intended. Moreover, in some cases, the data transfer control circuit as shown in FIG. 1 is to be used not solely to control data transfer. For example, the data transfer circuit may be useful in connection with logic circuits and the like for implementing data processing between latch circuits as shown in the pipeline system in FIG. 4. In most such instances, use of send and acknowledge lines is also desirable to provide a means for communication between processing stages. When configuring a pipeline system provided with multistage cascade connections, the wiring lengths of the send lines and acknowledge lines become long as the physical distance between stages become long. Since the wiring capacity increases proportionally to the wiring length, if the driving element is a MOS element, the delay time due to wiring cannot be ignored.
In addition, when a one-shot pulse circuit such as the D flip-flop is inserted into each stage, additional problems will be created, such as increase in the quantity of in-line hardware and reduction of the pulse transfer speed of the send signal. Furthermore, a D flip-flop circuit includes numerous logic gates and inverters and requires multiple data, clock, and other input signals as is well known in the art. Thus, to actually manufacture a D flip-flop for inclusion in a handshake circuit requires relatively complicated fabrication steps with a disadvantageous increase in costs.